Testovatelnost a fyzická bezpečnost: řešení na úrovni standardních buněk

Abstract

Reliability, testability, and security belong to the most signifcant digital design challenges. Notable testability and security problems originate at the physical level, while the solutions may be implemented at higher levels. This dissertation thesis deals with low-level approaches addressing the high-level design problems, namely the problem of the oine test length and fault coverage, and the problem of the physical security. The proposed solutions are based on enhanced CMOS structures. This dissertation thesis includes also a vulnerability analysis of the conventional CMOS circuit static power and established dynamic power countermeasures such as WDDL or SecLib. A particular contribution touches also on the security-reliability interplay.

Reliability, testability, and security belong to the most signifcant digital design challenges. Notable testability and security problems originate at the physical level, while the solutions may be implemented at higher levels. This dissertation thesis deals with low-level approaches addressing the high-level design problems, namely the problem of the oine test length and fault coverage, and the problem of the physical security. The proposed solutions are based on enhanced CMOS structures. This dissertation thesis includes also a vulnerability analysis of the conventional CMOS circuit static power and established dynamic power countermeasures such as WDDL or SecLib. A particular contribution touches also on the security-reliability interplay.