Spolehlivé architektury FPGA
Reliable FPGA Architecture
Typ dokumentu
disertační prácedoctoral thesis
Autor
Jan Pospíšil
Vedoucí práce
Schmidt Jan
Oponent práce
Drutarovský Miloš
Studijní obor
InformatikaStudijní program
InformatikaInstituce přidělující hodnost
katedra číslicového návrhuPráva
A university thesis is a work protected by the Copyright Act. Extracts, copies and transcripts of the thesis are allowed for personal use only and at one?s own expense. The use of thesis should be in compliance with the Copyright Act http://www.mkcr.cz/assets/autorske-pravo/01-3982006.pdf and the citation ethics http://knihovny.cvut.cz/vychova/vskp.htmlVysokoškolská závěrečná práce je dílo chráněné autorským zákonem. Je možné pořizovat z něj na své náklady a pro svoji osobní potřebu výpisy, opisy a rozmnoženiny. Jeho využití musí být v souladu s autorským zákonem http://www.mkcr.cz/assets/autorske-pravo/01-3982006.pdf a citační etikou http://knihovny.cvut.cz/vychova/vskp.html
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fields of electronics. The most prevalent type is SRAM-based, which uses static RAM cells to store its configuration. The inherent drawback of this technology is its susceptibility to Single Event Effects. The Single Event Upset is the main concern, which can result not only in corrupted data being processed, but also in a major change to the design function and connections. Mitigation techniques are known to handle this issue, but their impact evaluation is not always easy. The actual impact to the reliability of a given design needs to be evaluated taking into account not only changes made to the design on the Register-Transfer Level, but also the actual implementation of the design on a given FPGA. In our work, the main focus is on the FPGA architecture and its reliability in terms of radiation induced soft errors. We provide an overview of all the background needed to successfully handle this issue in this thesis. Later, an overview of the related works dealing with the similar topics and also connected research are presented. The method for a simulation-based evaluation of radiation induced soft errors in the SRAM-based FPGA configuration memory is proposed, an example implementation of this method on a chosen FPGA family is described, and individual steps are explained. Results of this example implementation on a set of benchmarks are presented and discussed. fields of electronics. The most prevalent type is SRAM-based, which uses static RAM cells to store its configuration. The inherent drawback of this technology is its susceptibility to Single Event Effects. The Single Event Upset is the main concern, which can result not only in corrupted data being processed, but also in a major change to the design function and connections. Mitigation techniques are known to handle this issue, but their impact evaluation is not always easy. The actual impact to the reliability of a given design needs to be evaluated taking into account not only changes made to the design on the RegisterTransfer Level, but also the actual implementation of the design on a given FPGA. In our work, the main focus is on the FPGA architecture and its reliability in terms of radiation induced soft errors. We provide an overview of all the background needed to successfully handle this issue in this thesis. Later, an overview of the related works dealing with the similar topics and also connected research are presented. The method for a simulation-based evaluation of radiation induced soft errors in the SRAM-based FPGA configuration memory is proposed, an example implementation of this method on a chosen FPGA family is described, and individual steps are explained. Results of this example implementation on a set of benchmarks are presented and discussed.