Automatické generování testovacích vektorů s nulovým maskováním pro obecný kompaktor odezvy

Abstract

D˚uleˇzitost a obt´ıˇznost testov´an´ı souˇcasn´ych ˇc´ıslicov´ych obvod˚u roste se zvyˇsuj´ıc´ı se komplexitou dneˇsn´ıch obvod˚u. Tato disertaˇcn´ı pr´ace m´a 2 t´emata. Hlavn´ım t´ematem je generov´an´ı testu s nulov´ym maskov´an´ım poruch v kompaktorech odezvy. Vedlejˇs´ım c´ılem je generov´an´ı testu pro aplikaˇcn´ı testov´an´ı obvod˚u implementovan´ych v FPGA ˇcipech. V prvn´ı ˇc´asti t´eto pr´ace je prezentov´an postup pro generov´an´ı testu pro aplikaˇcn´ı testov´an´ı obvod˚u FPGA. Je navrˇzen algoritmus vyuˇz´ıvaj´ıc´ı kombinovan´eho poruchov´eho modelu s poruchami trval´a nula a zmˇena bitu. Tyto poruchov´e modely, jejich vlastnosti a vz´ajemn´y vztah jsou analyzov´any. Tento v´ystup poskytuje nutn´e n´astroje a postupy pro dalˇs´ı v´yzkum: hlavn´ı t´ema t´eto pr´ace i pokraˇcuj´ıc´ı v´yzkum aplikaˇcn´ıho testov´an´ı FPGA, kter´y nen´ı souˇc´ast´ı t´eto pr´ace. V druh´e ˇc´asti t´eto pr´ace je prezentov´an algoritmus pro generov´an´ı testu s nulov´ym maskov´an´ım poruch v kompaktorech odezvy. Kompakce odezvy je d˚uleˇzit´y n´astroj v testov´an´ı obvod˚u a v n´avrhu pro testovatelnost. Kompakce zmenˇsuje mnoˇzstv´ı dat, kter´a je nutn´e pˇren´est z testovan´eho obvodu, za cenu vzniku maskov´an´ı poruch. Typick´e metody pro potlaˇcen´ı maskov´an´ı jsou ´uprava jiˇz existuj´ıc´ıho testu, nebo zmˇena n´avrhu kompaktoru. Navrˇzen´y algoritmus je schopn´y pˇr´ımo vytvoˇrit test se sn´ıˇzen´ym maskov´an´ım beze zmˇeny v n´avrhu kompaktoru. To vede k vyˇsˇs´ımu poruchov´emu pokryt´ı, pˇr´ıpadnˇe k moˇznosti pouˇzit´ı menˇs´ıch kompaktor˚u. Hlavn´ı pˇr´ınosy t´eto pr´ace jsou n´asleduj´ıc´ı: 1. Postup pro zak´odov´an´ı poruchov´eho modelu zmˇenˇen´eho bitu v aplikaˇcn´ım testov´an´ı obvod˚u FPGA. 2. Algoritmus pro generov´an´ı testu s nulov´ym maskov´an´ım pro obecn´y sekvenˇcn´ı kompaktor odezvy.

Testing of digital circuits is increasingly important and complex, as the size and complexity of contemporary circuits increase. Two topics related to digital circuit testing are the aim of this dissertation thesis. The main topic is a generation of test sets with zero aliasing in temporal compactors. The secondary topic is a generation of test sets for applicationoriented testing of field-programable gate arrays. An approach to test generation of application-oriented tests for circuits implemented in FPGAs is presented. An ATPG natively using a combined fault model of stuck-at and bitflip faults is proposed. The properties and relations of the two fault models are analyzed. This work forms a basis and provides necessary tools for subsequent research, the main aim of this thesis, and also further research on application-oriented FPGA testing that is not part of this thesis. An algorithm for generating tests with zero fault aliasing in output response compactors is proposed. Output response compaction is an important tool in digital circuit testing and design for testability techniques. The compaction decreases the amount of data needed to be transferred from the tested circuit, at the price of introducing fault aliasing. Typical methods to reduce fault aliasing include manipulating existing tests or changing the compactor design. The proposed method is able to directly generate tests with reduced aliasing without changing the compactor design. This leads to higher fault coverage and possibly smaller compactors. In particular, the main contributions of the dissertation thesis are as follows: 1. An encoding scheme for bit-flip fault model for application-oriented FPGA testing. 2. Algorithm for generating a zero-aliasing test for general output response compactor.