Show simple item record



dc.contributor.authorLerner, Ralf
dc.contributor.authorHansen, Nis Hauke
dc.date.accessioned2021-11-11T10:03:30Z
dc.date.available2021-11-11T10:03:30Z
dc.date.issued2021
dc.identifier.isbn978-80-01-06875-5
dc.identifier.urihttp://hdl.handle.net/10467/98494
dc.description.abstractSeveral approaches for close integration of power switches with CMOS logic are subject of technical evaluations and academic discussions. This paper identifies the commercially relevant processing steps of different integration methods (HV and SOI CMOS, monolithic integration in SOI and in GaN, Direct Wafer Bonding, micro-Transfer-Printing of GaN on CMOS and CMOS on GaN) and compares them on simple cost per wafer and cost per chip models. Four examples of real ICs verify the simple costs per chip model. Commercially attractive high voltage to logic partitionings are identified for the different integration approaches.en
dc.language.isoenen
dc.publisherČeské vysoké učení technické v Praze. České centrum IETcze
dc.titleCommercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printingen
dc.title.alternative15th INTERNATIONAL SEMINAR ON POWER SEMICONDUCTORS
dc.typestať ve sborníkucze
dc.typeconference paperen
dc.identifier.doi10.14311/ISPS.2021.015


Files in this item



This item appears in the following Collection(s)

Show simple item record