ZATPG: SAT-based ATPG for Zero-Aliasing Compaction
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One of long-standing problems in digital circuit testing is fault aliasing in the response compaction. Fault aliasing is an important source of coverage loss, especially if we strive to achieve high compaction ratio. Existing methods to lower or eliminate aliasing mostly require changes to the compactor design. This can lead to a higher compactor complexity, bigger area overhead, longer propagation paths, etc. We propose a method to eliminate aliasing without the need to modify the compactor design. The basic idea is to constrain the test pattern generation itself to produce a test with zero aliasing. This is in contrast to previous methods, where a test is computed independently and the anti-aliasing algorithm does not modify the test further [1, 2]. Some anti-aliasing algorithms exert a partial control over a test sequence, by reordering (already existing) test [3–5]. Note that we are only considering aliasing in a temporal compactor. Preventing aliasing in a spatial compactor is much easier problem, for both pre-existing and new test set. In our paper, we assume a spatial compactor that does not introduce new redundant faults.
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