Prohlížení Publikační činnost ČVUT dle předmětu "SAT"

Zobrazují se záznamy 1-4 z 4

    • Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing 

      Autor: Borecký J.; Hülle R.; Fišer P.
      (IEEE Computer Soc., 2020)
      Testing of FPGA-based designs persists to be a challenging task because of the complex FPGA architecture with heterogeneous components, and therefore a complicated fault model. The standard stuck-at fault model has been ...

    • SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support 

      Autor: Fišer P.; Háleček I.; Schmidt J.; Šimek V.
      (World Scientific Publishing, Ltd., 2019)
      This paper presents a method for generating optimum multi-level implementations of Boolean functions based on Satisfiability (SAT) and Pseudo-Boolean Optimization (PBO) problems solving. The method is able to generate one ...

    • ZATPG: SAT-based ATPG for Zero-Aliasing Compaction 

      Autor: Hülle R.; Fišer P.; Schmidt J.
      (ČVUT v Praze, Fakulta informačních technologií, 2018)
      One of long-standing problems in digital circuit testing is fault aliasing in the response compaction. Fault aliasing is an important source of coverage loss, especially if we strive to achieve high compaction ratio. ...

    • ZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compaction 

      Autor: Hülle R.; Fišer P.; Schmidt J.
      (Elsevier Science, 2018)
      Aliasing in test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing mostly require modification of the compactor to some extent. This can lead to a higher compactor complexity ...