A spatial systematic mismatch, occurring in the
integrated circuit manufacturing process, leads to differences
in parameters for two or more identical devices. It is widely
accepted that placing devices into symmetrical patterns reduces
the spatial systematic mismatch between their parameters. In this
paper, a novel method based on linear and nonlinear parameter
gradient modeling for the assessment of pre-arranged matched
structures has been proposed. The direction of a parameter
gradient against a layout topology on a wafer is unknown.
The pre-arranged layout pattern is rotated against the modeled
parameter gradient. In each step of the rotation, for example,
with a 1-degree resolution, the mismatch between parameters
is calculated. The peak mismatch value is then used for the
comparison of the different pre-arranged patterns. The proposed
method is independent of technology.
