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dc.contributor.authorHülle R.
dc.contributor.authorFišer P.
dc.contributor.authorSchmidt J.
dc.date.accessioned2020-02-24T17:24:39Z
dc.date.available2020-02-24T17:24:39Z
dc.date.issued2018
dc.identifierV3S-321779
dc.identifier.citationHÜLLE, R., P. FIŠER, and J. SCHMIDT. ZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compaction. Microprocessors and Microsystems. 2018, 2018(61), 43-57. ISSN 0141-9331. DOI 10.1016/j.micpro.2018.05.001.
dc.identifier.issn0141-9331 (print)
dc.identifier.issn1872-9436 (online)
dc.identifier.urihttp://hdl.handle.net/10467/86933
dc.description.abstractAliasing in test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing mostly require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc. In contrast to this standard approach, we propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing for any compactor used, thus without need of the compactor modification or redesign. This is achieved by constraining the test pattern generation process (ATPG), so that patterns exhibiting no aliasing are produced directly. Aliasing in both the spatial and temporal compactors is assumed. The method is based on modification of very basic SAT-based ATPG principles, thus any SAT-based ATPG can be used for its purpose. Also, the method is general enough to be applicable to any compactor design. We demonstrate our method on MISR compactors based on LFSR and cellular automata, using the single stuck-at fault model. Our method is able to find a test with zero aliasing and complete fault coverage for smaller compactors than a conventional, unguided ATPG. Thus, the area overhead of the compactor can be reduced, while the complete fault coverage is preserved.eng
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.publisherElsevier Science
dc.relation.ispartofMicroprocessors and Microsystems
dc.relation.urihttps://www.sciencedirect.com/science/article/pii/S0141933118300966
dc.subjectATPGeng
dc.subjectresponse compactioneng
dc.subjectaliasingeng
dc.subjectstuck-at faulteng
dc.subjectSATeng
dc.subjectzero aliasingeng
dc.subjectLFSReng
dc.subjectMISReng
dc.titleZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compactioneng
dc.typečlánek v časopisecze
dc.typejournal articleeng
dc.identifier.doi10.1016/j.micpro.2018.05.001
dc.relation.projectidinfo:eu-repo/grantAgreement/Czech Science Foundation/GA/GA16-05179S/CZ/Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features/
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/OPVVV/CZ.02.1.01%2F0.0%2F0.0%2F16_019%2F0000765/CZ/Research Center for Informatics/-
dc.rights.accessrestrictedAccess
dc.identifier.wos000441486700005
dc.type.statusPeer-reviewed
dc.type.versionpublishedVersion
dc.identifier.scopus2-s2.0-85048504988


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