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dc.contributor.authorMašek V.
dc.contributor.authorNovotný M.
dc.date.accessioned2022-04-10T14:26:50Z
dc.date.available2022-04-10T14:26:50Z
dc.date.issued2022
dc.identifierV3S-357690
dc.identifier.citationMAŠEK, V. and M. NOVOTNÝ. Versatile Hardware Framework for Elliptic Curve Cryptography. In: BĚLOHOUBEK, J. and J. BORECKÝ, eds. Proceedings of the 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Praha, 2022-04-06/2022-04-08. Piscataway: IEEE, 2022. p. 80-83. ISSN 2473-2117. ISBN 978-1-6654-9431-1.
dc.identifier.isbn978-1-6654-9431-1 (online)
dc.identifier.issn2473-2117 (online)
dc.identifier.urihttp://hdl.handle.net/10467/100534
dc.description.abstractWe propose versatile hardware framework for ECC. The framework supports arithmetic operations over P-256, Ed25519 and Curve25519 curves, enabling easy implementation of various ECC algorithms. Framework finds its application area e.g. in FIDO2 attestation or in nowadays rapidly expanding field of hardware wallets. As the design is intended to be ASIC-ready, we designed it to be area efficient. Hardware units are reused for calculations in several finite fields, and some of them are superior to previously designed circuits in terms of time-area product. The framework implements several attack countermeasures. It enables implementation of certain countermeasures even in later stages of design. The design was validated on SoC FPGA.eng
dc.format.mimetypeapplication/pdf
dc.language.isoeng
dc.publisherIEEE
dc.relation.ispartofProceedings of the 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
dc.subjectElliptic curve cryptographyeng
dc.subjectPublic key cryptog- raphyeng
dc.subjectSide channel hardeningeng
dc.subjectECDHeng
dc.subjectEdDSAeng
dc.subjectECDSAeng
dc.subjectFPGAeng
dc.titleVersatile Hardware Framework for Elliptic Curve Cryptographyeng
dc.typestať ve sborníkucze
dc.typeconference papereng
dc.relation.projectidinfo:eu-repo/grantAgreement/Ministry of Interior/VJ/VJ02010010/CZ/Tools for AI-enhanced Security Verification of Cryptographic Devices/AI-SecTools
dc.rights.accessopenAccess
dc.type.statusPeer-reviewed
dc.type.versionacceptedVersion
dc.relation.conference25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems


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