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dc.contributor.authorMitéran, J.
dc.contributor.authorMatas, J.
dc.contributor.authorDubois, J.
dc.contributor.authorBourennane, E.
dc.date.accessioned2012-06-07T11:24:09Z
dc.date.available2012-06-07T11:24:09Z
dc.date.issued2004
dc.identifier.citationJohel Miteran, Jiri Matas, Julian Dubois, and Elbey Bourennane. Automatic fpga based implementation of a classification tree. In IEEE SCS: Proceedings of the 1st International Conference on "Signaux, Circuits et Systemes", pages 188-192, 10662 Los Vaqueros Circle, P.O.Box 3014, CA 90720-1314, Los Alamitos, USA, March 2004. L'Ecole Nationale d'Ingénieurs de Sfax, France, IEEE Computer Society.cze
dc.identifier.urihttp://hdl.handle.net/10467/9492
dc.description.abstractWe propose a method of automatic hardware implementation of a decision rule based on the Adaboost algorithm. We review the principles of the classification method and we evaluate its hardware implementation cost in term of FPGA’s slice, using different weak classifiers based on the general concept of hyperrectangle. We show how to combine the weak classifiers in order to find a good trade-off between classification performances and hardware implementation cost. We present results obtained using examples coming from UCI databases.eng
dc.language.isocescze
dc.publisherIEEEcze
dc.rights© 2004 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.eng
dc.subjectAdaboosteng
dc.subjectFPGAeng
dc.subjectclassificationeng
dc.subjecthardwareeng
dc.subjectimage segmentationeng
dc.titleAutomatic FPGA based implementation of a classification treecze
dc.typepříspěvek z konference - elektronickýcze


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