Prohlížení Publikační činnost ČVUT dle autora "Fišer P."

Zobrazují se záznamy 1-10 z 10

    • Asynchronous sum-of-products logic minimization and orthogonalization 

      Autor: Lemberski I.; Fišer P.; Suleimanov R.
      (John Wiley & Sons, Inc., 2014)
      We propose a method of the asynchronous sum-of-products (SOP) logic simplification that comprises of minimization and orthogonalization. The method is based on a transformation of the conventional single-rail SOP synchronous ...

    • Dual-Rail Asynchronous Logic Multi-Level Implementation 

      Autor: Lemberski I.; Fišer P.
      (Elsevier Science Publishers B.V., 2014)
      A synthesis flow oriented on producing the delay-insensitive dual-rail asynchronous logic is proposed. Within this flow, the existing synchronous logic synthesis tools are exploited to design technology independent single-rail ...

    • Error Masking Method Based On The Short-Duration Offline Test 

      Autor: Bělohoubek J.; Fišer P.; Schmidt J.
      (Elsevier Science, 2017)
      The method proposed in this article allows to construct error-masking fail-operational systems by com- bining time and area redundancy. In such a system, error detection is performed online, while error masking is achieved ...

    • Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing 

      Autor: Borecký J.; Hülle R.; Fišer P.
      (IEEE Computer Soc., 2020)
      Testing of FPGA-based designs persists to be a challenging task because of the complex FPGA architecture with heterogeneous components, and therefore a complicated fault model. The standard stuck-at fault model has been ...

    • On don't cares in test compression 

      Autor: Balcárek J.; Fišer P.; Schmidt J.
      (Elsevier Science, 2014)
      Both test compression tools and ATPGs directly producing compressed test greatly benefit from don’t care values present in the test. Actually, presence of these don’t cares is essential for success of the compression. ...

    • SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support 

      Autor: Fišer P.; Háleček I.; Schmidt J.; Šimek V.
      (World Scientific Publishing, Ltd., 2019)
      This paper presents a method for generating optimum multi-level implementations of Boolean functions based on Satisfiability (SAT) and Pseudo-Boolean Optimization (PBO) problems solving. The method is able to generate one ...

    • Standard Cell Tuning Enables Data-Independent Static Power Consumption 

      Autor: Bělohoubek J.; Fišer P.; Schmidt J.
      (IEEE, 2020)
      Physical attacks, namely invasive, observation and combined, represent a great challenge for today’s digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel ...

    • Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR 

      Autor: Háleček I.; Fišer P.; Schmidt J.
      (Elsevier, 2018)
      Although contemporary logic synthesis performs well on random logic, it may produce subpar results in XOR-intensive circuits. This indicated the need of equal status of XORs and ANDs, with their respective Negation-Permu ...

    • ZATPG: SAT-based ATPG for Zero-Aliasing Compaction 

      Autor: Hülle R.; Fišer P.; Schmidt J.
      (ČVUT v Praze, Fakulta informačních technologií, 2018)
      One of long-standing problems in digital circuit testing is fault aliasing in the response compaction. Fault aliasing is an important source of coverage loss, especially if we strive to achieve high compaction ratio. ...

    • ZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compaction 

      Autor: Hülle R.; Fišer P.; Schmidt J.
      (Elsevier Science, 2018)
      Aliasing in test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing mostly require modification of the compactor to some extent. This can lead to a higher compactor complexity ...