Návrh QSPI master rozhraní
Design of QSPI master interface
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České vysoké učení technické v Praze
Czech Technical University in Prague
Czech Technical University in Prague
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Tato diplomová práce pojednává o návrhu a implementaci QSPI master rozhraní s procesorovým jádrem RISCV. QSPI protokol byl prostudován z dostupných flash pamětí, které QSPI rozhraní podporují. Byly porovnány rozdíly v protokolu mezi různými flash paměťmi a sestaven jednotný popis protokolu. Dále bylo prostudováno RISCV PULP rozhraní, aby k němu bylo možné připojit QSPI master rozhraní. Protokolové funkce a parametry byly vybrány a byl vytvořen systémový návrh a specifikace. Jednotlivé bloky návrhu byly implementovány na RTL úrovni pomocí VHDL. Během VHDL implementace byl návrh průběžně testován pomocí VHDL testů. Ověření konceptu návrhu bylo provedeno implementací QSPI master rozhraní společně RISCV procesorem do FPGA. Procesor byl naprogramován a byla ověřena komunikace mezi procesorem a QSPI rozhraním. Dále byla ověřena komunikace mezi QSPI rozhraním a připojenou externí flash pamětí. Na závěr byly pomocí UVM verifikačního prostředí testovány základní scénáře použití. Návrh je tím připraven na rozsáhlé testování.
This master's thesis deals with the design and implementation of the QSPI master interface with the RISCV processor core. The QSPI protocol was studied from available flash memories, which support QSPI protocol. Differences in the protocol were compared between studied flash memories, and a unified protocol description was written. The RISCV PULP interface was studied to allow connection of the RISCV with the QSPI master interface. Protocol features and parameters were chosen, and system-level design and design specification was created. Individual blocks of the design were implemented in RTL with VHDL. The design was continuously tested during the VHDL implementation phase with the VHDL testbench. Proof of concept was done by the implementation of the design with the RISCV processor into FPGA. The processor was programmed, and communication between the QSPI interface and the processor was verified. The QSPI communication was verified between the~QSPI interface and external flash memory. At last, basic use-cases were verified in the UVM environment implemented in System Verilog. Thereby, the design was prepared for full verification.
This master's thesis deals with the design and implementation of the QSPI master interface with the RISCV processor core. The QSPI protocol was studied from available flash memories, which support QSPI protocol. Differences in the protocol were compared between studied flash memories, and a unified protocol description was written. The RISCV PULP interface was studied to allow connection of the RISCV with the QSPI master interface. Protocol features and parameters were chosen, and system-level design and design specification was created. Individual blocks of the design were implemented in RTL with VHDL. The design was continuously tested during the VHDL implementation phase with the VHDL testbench. Proof of concept was done by the implementation of the design with the RISCV processor into FPGA. The processor was programmed, and communication between the QSPI interface and the processor was verified. The QSPI communication was verified between the~QSPI interface and external flash memory. At last, basic use-cases were verified in the UVM environment implemented in System Verilog. Thereby, the design was prepared for full verification.