PLC program verification
Verifikace programů pro PLC
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České vysoké učení technické v Praze
Czech Technical University in Prague
Czech Technical University in Prague
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Abstract
Tato práce se zabývá analýzou a kontrolou PLC programu. Její soucástí je nástroj pro automatické generování binárních rozhodovacích diagramu a stavových automatu pro promenné, které jsou použity v PLC programu. Hlavním cílem práce je prevést program napsaný v Ladder Diagramu prímo do BDD a stavového automatu. Kontrola programu je provedena prevedením do UPPAAL a následnou verifikací.
This thesis is about analyzing and verification of PLC program. There is also an instrument for automatical generating of binar decision diagram and for state machines for variables which are used in PLC program. Main result of thesis is translation of program in Ladder Diagram into BDD and state machine. Verification of the program is made by translation of state machine into UPPAAL.
This thesis is about analyzing and verification of PLC program. There is also an instrument for automatical generating of binar decision diagram and for state machines for variables which are used in PLC program. Main result of thesis is translation of program in Ladder Diagram into BDD and state machine. Verification of the program is made by translation of state machine into UPPAAL.