Zynq UltraScale+ Summary Report
User Configurations
MIO Configurations

CLK Configurations

DDR Configurations

GT Configurations
This design is targeted for xczu9eg board (part number: ES2-2)

## Zynq UltraScale+ Design Summary

Device | xczu9eg
SpeedGrade | -2
Part | ES2-2
Description | Zynq UltraScale+ PS Configuration Report
Vendor | Xilinx

## MIO Table View

MIO Pin | Peripheral | Signal | IO Type | Speed | Pullup | Direction | Drive Strength(mA)
MIO 0 |  |  | schmitt | slow | pullup |  | 12
MIO 1 |  |  | schmitt | slow | pullup |  | 12
MIO 2 |  |  | schmitt | slow | pullup |  | 12
MIO 3 |  |  | schmitt | slow | pullup |  | 12
MIO 4 |  |  | schmitt | slow | pullup |  | 12
MIO 5 |  |  | schmitt | slow | pullup |  | 12
MIO 6 |  |  | schmitt | slow | pullup | out | 12
MIO 7 |  |  | schmitt | slow | pullup | out | 12
MIO 8 |  |  | schmitt | slow | pullup |  | 12
MIO 9 |  |  | schmitt | slow | pullup |  | 12
MIO 10 |  |  | schmitt | slow | pullup |  | 12
MIO 11 |  |  | schmitt | slow | pullup |  | 12
MIO 12 |  |  | schmitt | slow | pullup |  | 12
MIO 13 |  |  | schmitt | slow | pullup | inout | 12
MIO 14 |  |  | schmitt | slow | pullup | inout | 12
MIO 15 |  |  | schmitt | slow | pullup | inout | 12
MIO 16 |  |  | schmitt | slow | pullup | inout | 12
MIO 17 |  |  | schmitt | slow | pullup | inout | 12
MIO 18 | UART 0 | rxd | schmitt | slow | pullup | in | 12
MIO 19 | UART 0 | txd | schmitt | slow | pullup | out | 12
MIO 20 | UART 1 | txd | schmitt | slow | pullup | out | 12
MIO 21 | UART 1 | rxd | schmitt | slow | pullup | in | 12
MIO 22 |  |  | schmitt | slow | pullup | inout | 12
MIO 23 |  |  | schmitt | slow | pullup | inout | 12
MIO 24 |  |  | schmitt | slow | pullup | out | 12
MIO 25 |  |  | schmitt | slow | pullup | in | 12
MIO 26 |  |  | schmitt | slow | pullup |  | 12
MIO 27 |  |  | schmitt | slow | pullup |  | 12
MIO 28 |  |  | schmitt | slow | pullup |  | 12
MIO 29 |  |  | schmitt | slow | pullup |  | 12
MIO 30 |  |  | schmitt | slow | pullup |  | 12
MIO 31 |  |  | schmitt | slow | pullup |  | 12
MIO 32 |  |  | schmitt | slow | pullup |  | 12
MIO 33 |  |  | schmitt | slow | pullup |  | 12
MIO 34 |  |  | schmitt | slow | pullup |  | 12
MIO 35 |  |  | schmitt | slow | pullup |  | 12
MIO 36 |  |  | schmitt | slow | pullup |  | 12
MIO 37 |  |  | schmitt | slow | pullup |  | 12
MIO 38 |  |  | schmitt | slow | pullup |  | 12
MIO 39 |  |  | schmitt | slow | pullup |  | 12
MIO 40 |  |  | schmitt | slow | pullup |  | 12
MIO 41 |  |  | schmitt | slow | pullup |  | 12
MIO 42 |  |  | schmitt | slow | pullup |  | 12
MIO 43 |  |  | schmitt | slow | pullup |  | 12
MIO 44 |  |  | schmitt | slow | pullup |  | 12
MIO 45 |  |  | schmitt | slow | pullup |  | 12
MIO 46 |  |  | schmitt | slow | pullup |  | 12
MIO 47 |  |  | schmitt | slow | pullup |  | 12
MIO 48 |  |  | schmitt | slow | pullup |  | 12
MIO 49 |  |  | schmitt | slow | pullup |  | 12
MIO 50 |  |  | schmitt | slow | pullup |  | 12
MIO 51 |  |  | schmitt | slow | pullup |  | 12
MIO 52 | USB 0 | ulpi_clk_in | schmitt | slow | pullup | in | 12
MIO 53 | USB 0 | ulpi_dir | schmitt | slow | pullup | in | 12
MIO 54 | USB 0 | ulpi_tx_data[2] | schmitt | slow | pullup | inout | 12
MIO 55 | USB 0 | ulpi_nxt | schmitt | slow | pullup | in | 12
MIO 56 | USB 0 | ulpi_tx_data[0] | schmitt | slow | pullup | inout | 12
MIO 57 | USB 0 | ulpi_tx_data[1] | schmitt | slow | pullup | inout | 12
MIO 58 | USB 0 | ulpi_stp | schmitt | slow | pullup | out | 12
MIO 59 | USB 0 | ulpi_tx_data[3] | schmitt | slow | pullup | inout | 12
MIO 60 | USB 0 | ulpi_tx_data[4] | schmitt | slow | pullup | inout | 12
MIO 61 | USB 0 | ulpi_tx_data[5] | schmitt | slow | pullup | inout | 12
MIO 62 | USB 0 | ulpi_tx_data[6] | schmitt | slow | pullup | inout | 12
MIO 63 | USB 0 | ulpi_tx_data[7] | schmitt | slow | pullup | inout | 12
MIO 64 |  |  | schmitt | slow | pullup |  | 12
MIO 65 |  |  | schmitt | slow | pullup |  | 12
MIO 66 |  |  | schmitt | slow | pullup |  | 12
MIO 67 |  |  | schmitt | slow | pullup |  | 12
MIO 68 |  |  | schmitt | slow | pullup |  | 12
MIO 69 |  |  | schmitt | slow | pullup |  | 12
MIO 70 |  |  | schmitt | slow | pullup |  | 12
MIO 71 |  |  | schmitt | slow | pullup |  | 12
MIO 72 |  |  | schmitt | slow | pullup |  | 12
MIO 73 |  |  | schmitt | slow | pullup |  | 12
MIO 74 |  |  | schmitt | slow | pullup |  | 12
MIO 75 |  |  | schmitt | slow | pullup |  | 12
MIO 76 |  |  | schmitt | slow | pullup | out | 12
MIO 77 |  |  | schmitt | slow | pullup | inout | 12

## PS Clocks information

PSS REF CLK : 33.330

Name | Source | Input Frequency (MHz)
APLL | PSS_REF_CLK | 2399.760
DPLL | PSS_REF_CLK | 2133.120
VPLL | PSS_REF_CLK | 2999.700
RPLL | PSS_REF_CLK | 2999.700
IOPLL | PSS_REF_CLK | 1999.800

Peripheral | Requested Frequency (MHz) | Source | Actual Frequency (MHz)
USB0 freq (MHz) | 250 | IOPLL | 249.975000
UART0 freq (MHz) | 100 | IOPLL | 99.990000
UART1 freq (MHz) | 100 | IOPLL | 99.990000
CPU_R5 freq (MHz) | 500 | IOPLL | 499.950000
IOU_SWITCH freq (MHz) | 250 | IOPLL | 249.975000
LPD_SWITCH freq (MHz) | 500 | IOPLL | 499.950000
LPD_LSBUS freq (MHz) | 100 | IOPLL | 99.990000
TIMESTAMP freq (MHz) | 100 | IOPLL | 99.990000
PSU__CRL_APB__USB3_REF_CTRL__freqmhz | 20 | IOPLL | 19.998000
PCAP freq (MHz) | 200 | IOPLL | 199.980000
DBG_LPD freq (MHz) | 250 | IOPLL | 249.975000
ADMA freq (MHz) | 500 | IOPLL | 499.950000
PL0 freq (MHz) | 100 | IOPLL | 99.990000
AMS freq (MHz) | 52 | IOPLL | 49.995000
ACPU freq (MHz) | 1200 | APLL | 1199.880000
DBG FPD freq (MHz) | 250 | IOPLL | 249.975000
DDR_CTRL freq MHz) | 533.500 | DPLL | 533.280000
GPU freq (MHz) | 500 | IOPLL | 499.950000
GDMA freq (MHz) | 600 | APLL | 599.940000
DPDMA freq (MHz) | 600 | APLL | 599.940000
TOPSW_MAIN freq (MHz) | 533.33 | DPLL | 533.280000
TOPSW_LSBUS freq (MHz) | 100 | IOPLL | 99.990000
DBG TSTMP freq (MHz) | 250 | IOPLL | 249.975000

## DDR Memory information

Parameter name | Value | Description
ENABLE | 1 | Enable the PS DDR Controller
DDR Interface freq (MHz) | 1067 | --
MEMORY TYPE | DDR 4 | Type of memory interface
DM DBI | UDIMM |
BUS WIDTH | 64 Bit | Data width of DDR interface, not including ECC data width
ECC | Disabled | Enables error correction code support
SPEED BIN | DDR4_2133P | Speed Bin
CL | 15 | Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL | 14 | CAS write latency setting in memory clock cycles
DDR AL | 0 | Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD | 15 | tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP | 15 | Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC | 47.06 | Row cycle time (ns)
T RAS MIN | 33 | Minimum number of memory clock cycles required between an Active and Precharge command
T FAW | 30.0 | Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH | 8 Bits | Width of individual DRAM components
DEVICE CAPACITY | 4096 MBits | Storage capacity of individual DRAM components
BG ADDR COUNT | 2 | Number of bank group address pins
RANK ADDR COUNT | 0 | Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT | 2 | Number of bank address pins
ROW ADDR COUNT | 15 | Number of row address pins
COL ADDR COUNT | 10 | Number of column address bits
C_DDR_RAM_HIGHADDR | 0xFFFFFFFF | --

## GT lanes information

Protocol | GT lane# | Ref Clk Sel | Ref freq (MHz)
USB0 | GT Lane2 | Ref Clk2 | 26