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==The medium was uploaded to alternative storage assigned by FIT ICT.
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This medium contains all materials for the Falcon SamplerZ FPGA accelerator thesis.

Top-level items
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* exe/ – ready-to-use executable / bitstream build of the accelerator.
* repo/ – complete implementation repository  
  * scripts/ – TCL scripts that (re)create the Vivado project.  
  * misc/ – assorted helper files and notes.  
  * src/ – hardware sources  
    * bd/ – Vivado block-design (.bd) files  
    * constr/ – XDC constraints (pins, timing)  
    * flopoco/ – parameterised arithmetic cores generated with FloPoCo  
    * hdl/ – hand-written VHDL/Verilog code  
    * ip/ – packaged IP core definitions  
    * registers/ – Python register-map generator  
    * sim/ – test-benches and simulation models  
  * sw/ – C/C++ drivers and demo applications for the accelerator
* thesis/ – LaTeX sources of the written thesis
* thesis.pdf – final single-sided thesis PDF
* thesis-twoside.pdf – print-ready (two-sided) thesis PDF
* readme.txt – this file